The present invention relates to a semiconductor device, and more particularly to a semiconductor device with a high-precision capacitor.
Some semiconductor devices with an analog circuit require a high precision for capacitance ratio between multiple capacitors.
Japanese Patent Laid-Open No. 2004-146632 describes a technique by which a dummy line is formed in the same layer as an upper electrode and a lower electrode of a MIM (Metal-Insulator-Metal) capacitor, and a dummy line is also formed above the upper electrode and below the lower electrode, and these dummy lines are connected to the ground, whereby effects of noise on the capacitor are reduced.
Japanese Patent Laid-Open No. 2003-152085 describes a technique by which an upper shield layer is arranged above an upper electrode of a MIM capacitor, and a lower shield layer is arranged below a lower electrode, and the upper shield layer and the lower shield layer are connected via a via, whereby coupling of noise to the capacitor is prevented.
Further, Japanese Patent Laid-Open No. 2007-5719 describes a technique in which a MIM capacitor is used which includes an upper electrode, intermediate electrode and lower electrode, the upper electrode and the lower electrode being connected via a via, so that while the area occupied by the capacitor is reduced, parasitic capacitance of the capacitor is reduced.
Further, Japanese Patent Laid-Open No. 2007-184324 describes a capacitor including an intermediate electrode arranged between an upper electrode and lower electrode connected to a ground pad.
However, the above documents disclose neither a structure of capacitor in which, while excellent layout efficiency is kept, effects of noise from the capacitor is suppressed, nor arrangement of the capacitor, nor a method of connecting the capacitor.